Altera cyclone V Technical Reference page 1353

Hard processor system
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17-138
MAC_Configuration
31
30
Reserved
15
14
ps
fes
RW 0x0
RW
0x0
MAC_Configuration Fields
Bit
27
twokpe
25
cst
24
tc
Altera Corporation
29
28
27
26
twokp
Reser
e
ved
RW
0x0
13
12
11
10
do
lm
dm
ipc
RW
RW
RW
RW
0x0
0x0
0x0
0x0
Name
When set, the MAC considers all frames, with up to
2,000 bytes length, as normal packets. When Bit 20
(Jumbo Enable) is not set, the MAC considers all
received frames of size more than 2K bytes as Giant
frames. When this bit is reset and Bit 20 (Jumbo
Enable) is not set, the MAC considers all received
frames of size more than 1,518 bytes (1,522 bytes for
tagged) as Giant frames. When Bit 20 (Jumbo Enable)
is set, setting this bit has no effect on Giant Frame
status.
When set, the last 4 bytes (FCS) of all frames of Ether
type (type field greater than 0x0600) are stripped and
dropped before forwarding the frame to the applica‐
tion. This function is not valid when the IP Checksum
Engine (Type 1) is enabled in the MAC receiver.
Value
0x0
0x1
When set, this bit enables the transmission of duplex
mode, link speed, and link up or down information to
the PHY in the RGMII. When this bit is reset, no such
information is driven to the PHY.
Value
0x1
0x0
Bit Fields
25
24
23
22
cst
tc
wd
jd
RW
RW
RW
RW
0x0
0x0
0x0
0x0
9
8
7
6
dr
lud
acs
bl
RW
RW
RW
RW 0x0
0x0
0x0
0x0
Description
Description
Strip Ether Frames Off
Strip Ether Frames On
Description
Enables Transmission of duplex
Disables Transmission to Phy
21
20
19
18
be
je
ifg
RW
RW
RW 0x0
0x0
0x0
5
4
3
2
dc
te
re
RW
RW
RW
0x0
0x0
0x0
Access
Ethernet Media Access Controller
cv_5v4
2016.10.28
17
16
dcrs
RW 0x0
1
0
prelen
RW 0x0
Reset
RW
0x0
RW
0x0
RW
0x0
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