Altera cyclone V Technical Reference page 1382

cv_5v4
2016.10.28
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
Reserved
15 14
LPI_Timers_Control Fields
Bit
25:16
lst
15:0
twt
Interrupt_Status
The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt
events are generated only when the corresponding optional feature is enabled.
Module Instance
emac0
emac1
Offset:
0x38
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Ethernet Media Access Controller
Send Feedback
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This field specifies the minimum time (in millisec‐
onds) for which the link status from the PHY should
be up (OKAY) before the LPI pattern can be
transmitted to the PHY. The MAC does not transmit
the LPI pattern even when the LPIEN bit is set unless
the LPI LS Timer reaches the programmed terminal
count. The default value of the LPI LS Timer is 1000
(1 sec) as defined in the IEEE standard.
This field specifies the minimum time (in microsec‐
onds) for which the MAC waits after it stops
transmitting the LPI pattern to the PHY and before it
resumes the normal transmission. The TLPIEX status
bit is set after the expiry of this timer.
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
9 8 7 6
twt
RW 0x0
Description
Base Address
Interrupt_Status
21 20 19 18
lst
RW 0x3E8
5 4 3 2
Access
Register Address
0xFF700038
0xFF702038
17-167
17 16
1 0
Reset
RW 0x3E8
RW 0x0
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