Altera cyclone V Technical Reference page 1371

Hard processor system
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17-156
Flow_Control
Bit
5:4
plt
3
up
2
rfe
Altera Corporation
Name
This field configures the threshold of the PAUSE timer
at which the input flow control signal mti_​flowctrl_​i
(or sbd_​flowctrl_​i)​ is checked for automatic retrans‐
mission of PAUSE Frame. The threshold values
should be always less than the Pause Time configured
in Bits[31:16]. For example, if PT = 100H (256 slot-
times), and PLT = 01, then a second PAUSE frame is
automatically transmitted if the mti_​flowctrl_​i signal
is asserted at 228 (256 - 28) slot times after the first
PAUSE frame is transmitted. The slot time is defined
as the time taken to transmit 512 bits (64 bytes) on
the GMII or MII interface.
Value
0x0
0x1
0x2
0x3
When this bit is set, then in addition to the detecting
Pause frames with the unique multicast address, the
MAC detects the Pause frames with the station's
unicast address specified in the MAC Address0 High
Register and MAC Address0 Low Register. When this
bit is reset, the MAC detects only a Pause frame with
the unique multicast address specified in the 802.3x
standard.
Value
0x0
0x1
When this bit is set, the MAC decodes the received
Pause frame and disables its transmitter for a
specified (Pause) time. When this bit is reset, the
decode function of the Pause frame is disabled.
Value
0x0
0x1
Description
Description
Pause time - 4 slot times
Pause time - 28 slot times
Pause time - 144 slot times
Pause time - 256 slot times
Description
MAC Detects Pause MCA
MAC Detects Pause MCA and UCA
Description
Decode Func. of Pause Frame Disabled
MAC decodes the received Pause
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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