Altera cyclone V Technical Reference page 1359

17-144
MAC_Configuration
Bit
4
dc
3
te
2
re
Altera Corporation
Name
When this bit is set, the deferral check function is
enabled in the MAC. The MAC issues a Frame Abort
status, along with the excessive deferral error bit set in
the transmit frame status, when the transmit state
machine is deferred for more than 24,288 bit times in
the 10 or 100 Mbps mode. If the MAC is configured
for 1000 Mbps operation, or if the Jumbo frame mode
is enabled in the 10 or 100 Mbps mode, the threshold
for deferral is 155,680 bits times. Deferral begins
when the transmitter is ready to transmit, but is
prevented because of an active carrier sense signal
(CRS) on GMII or MII. Defer time is not cumulative.
When the transmitter defers for 10,000 bit times, it
transmits, collides, backs off, and then defers again
after completion of back-off. The deferral timer resets
to 0 and restarts. When this bit is reset, the deferral
check function is disabled and the MAC defers until
the CRS signal goes inactive. This bit is applicable
only in the half-duplex mode.
Value
0x1
0x0
When this bit is set, the transmit state machine of the
MAC is enabled for transmission on the GMII or MII.
When this bit is reset, the MAC transmit state
machine is disabled after the completion of the
transmission of the current frame, and does not
transmit any further frames.
Value
0x0
0x1
When this bit is set, the receiver state machine of the
MAC is enabled for receiving frames from the GMII
or MII. When this bit is reset, the MAC receive state
machine is disabled after the completion of the
reception of the current frame, and does not receive
any further frames from the GMII or MII.
Value
0x0
0x1
Description
Description
Deferral Check Enabled
Deferral Check Disabled
Description
MAC transmit state machine disabled
MAC transmit state machine enabled
Description
MAC receive state machine disabled
MAC receive state machine enabled
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
Ethernet Media Access Controller
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