Altera cyclone V Technical Reference page 1379

17-164
LPI_Control_Status
LPI_Control_Status Fields
Bit
19
lpitxa
18
plsen
17
pls
Altera Corporation
Name
This bit controls the behavior of the MAC when it is
entering or coming out of the LPI mode on the
transmit side. This bit is not functional in the GMAC-
CORE configuration in which the Tx clock gating is
done during the LPI mode. If the LPITXA and LPIEN
bits are set to 1, the MAC enters the LPI mode only
after all outstanding frames (in the core) and pending
frames have been transmitted. The MAC comes out of
the LPI mode when the application sends any frame
for transmission or the application issues a TX FIFO
Flush command. In addition, the MAC automatically
clears the LPIEN bit when it exits the LPI state. If TX
FIFO Flush is set, in Bit 20 of Register 6 (Operation
Mode Register), when the MAC is in the LPI mode,
the MAC exits the LPI mode. When this bit is 0, the
LPIEN bit directly controls behavior of the MAC
when it is entering or coming out of the LPI mode.
Value
0x0
0x1
This bit enables the link status received on the RGMII
receive paths to be used for activating the LPI LS
TIMER. When set, the MAC uses the link-status bits
of Register 54 (SGMII/RGMII/SMII Status Register)
and Bit 17 (PLS) for the LPI LS Timer trigger. When
cleared, the MAC ignores the link-status bits of
Register 54 and takes only the PLS bit.
Value
0x0
0x1
This bit indicates the link status of the PHY. The MAC
Transmitter asserts the LPI pattern only when the link
status is up (okay) at least for the time indicated by
the LPI LS TIMER. When set, the link is considered
to be okay (up) and when reset, the link is considered
to be down.
Value
0x0
0x1
Description
Description
LPI TX Automate Disabled
LPI TX Automate Enabled
Description
MAC Ignores Link Status Bits
MAC Uses Link Status Bits
Description
Link Down
Link Up (okay)
2016.10.28
Access Reset
RW 0x0
RW 0x0
RW 0x0
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