Altera cyclone V Technical Reference page 1384

cv_5v4
2016.10.28
Bit
7
mmcrxipis
6
mmctxis
5
mmcrxis
4
mmcis
2
pcsancis
Ethernet Media Access Controller
Send Feedback
Name
This bit is set high when an interrupt is generated in
the MMC Receive Checksum Offload Interrupt
Register. This bit is cleared when all the bits in this
interrupt register are cleared.
Value
0x0
0x1
This bit is set high when an interrupt is generated in
the MMC Transmit Interrupt Register. This bit is
cleared when all the bits in this interrupt register are
cleared.
Value
0x0
0x1
This bit is set high when an interrupt is generated in
the MMC Receive Interrupt Register. This bit is
cleared when all the bits in this interrupt register are
cleared.
Value
0x0
0x1
This bit is set high when any of the Bits [7:5] is set
high and cleared only when all of these bits are low.
Value
0x0
0x1
This bit is set when the Auto-negotiation is completed
in the TBI, RTBI, or SGMII PHY interface (Bit 5 in
Register 49 (AN Status Register)). This bit is cleared
when you perform a read operation to the AN Status
register. This bit is valid only when you select the
SGMII PHY interface during operation.
Description
Description
MMC Receive Checksum Offload Interrupt
Status Disabled
MMC Receive Checksum Offload Interrupt
Status Enabled
Description
MMC Transmit Interrupt Status Disabled
MMC Transmit Interrupt Status Enabled
Description
MMC Receive Interrupt Status Disabled
MMC Receive Interrupt Status Enabled
Description
MMC Interrupt Status Disabled
MMC Interrupt Status Enabled
17-169
Interrupt_Status
Access Reset
RO 0x0
RO 0x0
RO 0x0
RO 0x0
RO 0x0
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