Altera cyclone V Technical Reference page 1334

cv_5v4
2016.10.28
MAC_Address54_High
The MAC Address54 High register holds the upper 16 bits of the 55th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address54 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address54_Low
The MAC Address54 Low register holds the lower 32 bits of the 55th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address55_High
The MAC Address55 High register holds the upper 16 bits of the 56th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address55 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address55_Low
The MAC Address55 Low register holds the lower 32 bits of the 56th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address56_High
The MAC Address56 High register holds the upper 16 bits of the 57th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address56 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address56_Low
The MAC Address56 Low register holds the lower 32 bits of the 57th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address57_High
The MAC Address57 High register holds the upper 16 bits of the 58th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address57 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address57_Low
The MAC Address57 Low register holds the lower 32 bits of the 58th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
Ethernet Media Access Controller
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on page 17-537
on page 17-541
on page 17-541
on page 17-545
on page 17-545
on page 17-549
on page 17-549
on page 17-553
GMAC Register Group Register Descriptions
17-119
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