Altera cyclone V Technical Reference page 1358

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

cv_5v4
2016.10.28
Bit
7
acs
6:5
bl
Ethernet Media Access Controller
Send Feedback
Name
When this bit is set, the MAC strips the Pad or FCS
field on the incoming frames only if the value of the
length field is less than 1,536 bytes. All received
frames with length field greater than or equal to 1,536
bytes are passed to the application without stripping
the Pad or FCS field. When this bit is reset, the MAC
passes all incoming frames, without modifying them,
to the Host.
Value
0x0
0x1
The Back-Off limit determines the random integer
number (r) of slot time delays (4,096 bit times for
1000 Mbps and 512 bit times for 10/100 Mbps) for
which the MAC waits before rescheduling a transmis‐
sion attempt during retries after a collision. This bit is
applicable only in the half-duplex mode. * 00: k = min
(n, 10) * 01: k = min (n, 8) * 10: k = min (n, 4) * 11: k
= min (n, 1) where <i> n </i>= retransmission
attempt. The random integer <i> r </i> takes the
value in the range 0 <= r < kth power of 2
Value
0x0
0x1
0x2
0x3
Description
Description
Disable Automatic Pad CRC Stripping
Enable Automatic Pad CRC Stripping
Description
k = min (n, 10)
k = min (n, 8)
k = min (n, 4)
k = min (n, 1)
17-143
MAC_Configuration
Access
Reset
RW
0x0
RW
0x0
Altera Corporation

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents