Altera cyclone V Technical Reference page 1386

cv_5v4
2016.10.28
Interrupt_Mask Fields
Bit
10
lpiim
9
tsim
2
pcsancim
1
pcslchgim
0
rgsmiiim
MAC_Address0_High
The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station.
The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the
MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first
column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with
Ethernet Media Access Controller
Send Feedback
Name
When set, this bit disables the assertion of the
interrupt signal because of the setting of the LPI
Interrupt Status bit in Register 14 (Interrupt Status
Register).
Value
0x0
0x1
When set, this bit disables the assertion of the
interrupt signal because of the setting of Timestamp
Interrupt Status bit in Register 14 (Interrupt Status
Register).
Value
0x0
0x1
When set, this bit disables the assertion of the
interrupt signal because of the setting of PCS Auto-
negotiation complete bit in Register 14 (Interrupt
Status Register).
When set, this bit disables the assertion of the
interrupt signal because of the setting of the PCS
Link-status changed bit in Register 14 (Interrupt
Status Register).
When set, this bit disables the assertion of the
interrupt signal because of the setting of the RGMII
or SMII Interrupt Status bit in Register 14 (Interrupt
Status Register).
Value
0x0
0x1
Description
Description
LPI Interrupt Mask Disabled
LPI Interrupt Mask Enabled
Description
Timestamp Interrupt Mask Disabled
Timestamp Interrupt Mask Enabled
Description
RGMII or SMII Interrupt Mask Disable
RGMII or SMII Interrupt Mask Enable
17-171
MAC_Address0_High
Access Reset
RW 0x0
RW 0x0
RO 0x0
RO 0x0
RW 0x0
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