Altera cyclone V Technical Reference page 1264

cv_5v4
2016.10.28
Figure 17-14: Algorithm for System Time Update Using Fine Method
addend_val[31:0]
Addend Register
incr_sub_sec_reg
incr_sec_reg
The System Time Update logic requires a 50-MHz clock frequency to achieve 20-ns accuracy. The
frequency division ratio (FreqDivisionRatio) is the ratio of the reference clock frequency to the required
clock frequency. Hence, if the reference clock (
calculated as 66 MHz / 50 MHz = 1.32. Hence, the default addend value to program in the register is 232 /
1.32, 0xC1F07C1F.
If the reference clock drifts lower, to 65 MHz for example, the ratio is 65 / 50, or 1.3 and the value to set in
the addend register is 232 / 1.30, or 0xC4EC4EC4. If the clock drifts higher, to 67 MHz for example, the
addend register must be set to 0xBF0B7672. When the clock drift is nil, the default addend value of
0xC1F07C1F (232 / 1.32) must be programmed.
In the above figure, the constant value used to accumulate the sub-second register is decimal 43, which
achieves an accuracy of 20 ns in the system time (in other words, it is incremented in 20-ns steps).
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addend_updt
Accumulator Register
Constant Value
Sub-Second Register
Second Register
System Time Register Module
) is for example, 66 MHz, this ratio is
clk_ptp_ref_i
†
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