Altera cyclone V Technical Reference page 1355

Hard processor system
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17-140
MAC_Configuration
Bit
19:17
ifg
16
dcrs
15
ps
Altera Corporation
Name
These bits control the minimum IFG between frames
during transmission. In the half-duplex mode, the
minimum IFG can be configured only for 64 bit times
(IFG = 100). Lower values are not considered. In the
1000-Mbps mode, the minimum IFG supported is 80
bit times (and above).
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
When set high, this bit makes the MAC transmitter
ignore the (G)MII CRS signal during frame transmis‐
sion in the half-duplex mode. This request results in
no errors generated because of Loss of Carrier or No
Carrier during such transmission. When this bit is
low, the MAC transmitter generates such errors
because of Carrier Sense and can even abort the
transmissions.
Value
0x0
0x1
This bit selects between GMII and MII
Value
0x0
0x1
Description
Description
Inter Frame Gap 96 bit times
Inter Frame Gap 88 bit times
Inter Frame Gap 80 bit times
Inter Frame Gap 72 bit times
Inter Frame Gap 64 bit times
Inter Frame Gap 56 bit times
Inter Frame Gap 48 bit times
Inter Frame Gap 40 bit times
Description
MAC Tx Gen. Err. No Carrier
MAC Tx Ignores (G)MII Crs Signal
Description
GMII 1000 Mbps
MII 10/100 Mbps
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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