Altera cyclone V Technical Reference page 1377

Hard processor system

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When high, this bit indicates that the MAC GMII or

MII transmit protocol engine is actively transmitting

data and is not in the IDLE state.

This field gives the status of the fill-level of the Rx

This field gives the state of the Rx FIFO read

When high, this bit indicates that the MTL Rx FIFO

Write Controller is active and is transferring a

received frame to the FIFO.

Actively Transmitting Data

Rx FIFO Empty

Rx FIFO fill-level below flow-control

deactivate thres.

Rx FIFO fill-level above flow-control activate

Rx FIFO Full

Reading Frame Data

Reading Frame Status (or timestamp)

Flushing Frame Data and Status

MTL Rx Fifo Controller Non-Active Status

MTL Rx Fifo Controller Active Status

Ethernet Media Access Controller

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