Altera cyclone V Technical Reference page 1277

17-62
Clock Gating for EEE
Figure 17-15: EMAC Clock Diagram
Clock
l4_mp_clk
Manager
emac_ptp_ ref_clk
from FPGA
TXCLK from
FPGA MII
phy_intf_sel[1:0]
from System Manager
RX_CLK f r om
HPS I/O or FPGA
The diagram below summarizes the clock domains of the EMAC module:
Clock Gating for EEE
For the RGMII PHY interface, you can gate the transmit clock for Energy Efficient Ethernet (EEE) applica‐
tions.
Related Information
Programming Guidelines for Energy Efficient Ethernet
Reset
The EMAC module accepts a single reset input,
Note: In all modes, the EMAC core depends on the PHY clocks to be active for the internal EMAC clock
sources to be valid.
Taking the Ethernet MAC Out of Reset
When a cold or warm reset is issued in the HPS, the Reset Manager resets the EMAC module and holds it
in reset until software releases it.
After the MPU boots up, it can deassert the reset signal by clearing the appropriate bits in the Reset
Manager's corresponding reset register. Before deasserting the reset signal, you must make sure the PHY
Altera Corporation
emac*_clk
osc1_clk
clk_ptp_ ref_i
mux
2.5/25 MHz for MII
clk_tx_i
Divider
RMII Input
clk_rx_i
GMII/RGMII/MII Input
clk_tx_int
mux
2.5/25/125
MHz for MII
clk_rx_int
mux
on page 17-69
, which is active low.
emac_rst_n
RMII Output
clk_tx_o
EMAC
speed_sele c t
clk_rmii
clk_tx_i
clk_tx_i n v
phy_intf_sel[1]
phy_intf_sel[0]
clk_rx_i
clk_rx_inv
ap_clk
clk_csr_i
clk_ptp_ ref_i
Ethernet Media Access Controller
Send Feedback
cv_5v4
2016.10.28
TX_CLK
(to Pin
Mux/FPGA)