Altera cyclone V Technical Reference page 1383

Hard processor system

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Interrupt_Status

Interrupt_Status Fields

Altera Corporation

This bit is set for any LPI state entry or exit in the

MAC Transmitter or Receiver. This bit is cleared on

reading Bit 0 of Register 12 (LPI Control and Status

This bit is set when any of the following conditions is

true: * The system time value equals or exceeds the

value specified in the Target Time High and Low

registers. * There is an overflow in the seconds

This bit is cleared on reading Bit 0 of the Register 458

(Timestamp Status Register). When set, this bit

indicates that the system time value is equal to or

exceeds the value specified in the Target Time

registers. In this mode, this bit is cleared after the

completion of the read of this bit. In all other modes,

this bit is reserved.

LPI Interrupt Status Disabled

LPI Interrupt Status Enabled

Timestamp Interrupt Status Disabled

Timestamp Interrupt Status Enabled

Ethernet Media Access Controller

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