Altera cyclone V Technical Reference page 1309

17-94
GMAC Register Group Register Descriptions
Register
HW_Feature on page
17-868
GMAC Register Group Register Descriptions
GMAC Register Group
Offset:
0x0
MAC_Configuration
The MAC Configuration register establishes receive and transmit operating modes.
MAC_Frame_Filter
The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from
this register go to the address check block of the MAC, which performs the first level of address filtering.
The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad
Frames and Pass Control Frames.
GMII_Address
The GMII Address register controls the management cycles to the external PHY through the management
interface.
GMII_Data
The GMII Data register stores Write data to be written to the PHY register located at the address specified
in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register
located at the address specified by Register 4.
Flow_Control
The Flow Control register controls the generation and reception of the Control (Pause Command) frames
by the MAC's Flow control block. A Write to a register with the Busy bit set to '1' triggers the Flow Control
block to generate a Pause Control frame. The fields of the control frame are selected as specified in the
802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the
control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host
must make sure that the Busy bit is cleared before writing to the register.
VLAN_Tag
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC
compares the 13th and 14th bytes of the receiving frame (Length/Type) with 16'h8100, and the following
two bytes are compared with the VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the
receive frame status. The legal length of the frame is increased from 1,518 bytes to 1,522 bytes. Because the
VLAN Tag register is double-synchronized to the (G)MII clock domain, then consecutive writes to these
register should be performed only after at least four clock cycles in the destination clock domain.
Version on page 17-159
The Version registers identifies the version of the EMAC. This register contains two bytes: one specified by
Synopsys to identify the core release number, and the other specified by Altera.
Debug
on page 17-159
The Debug register gives the status of all main blocks of the transmit and receive data-paths and the
FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is
going on in the data-paths.
Altera Corporation
Offset Width Acces
0x1058
on page 17-137
on page 17-145
on page 17-151
on page 17-153
on page 17-154
on page 17-157
Reset Value
s
32 RO 0x70D69BF
Description
Register 22 (HW Feature Register)
Ethernet Media Access Controller
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cv_5v4
2016.10.28