Altera cyclone V Technical Reference page 1343

17-128
GMAC Register Group Register Descriptions
MAC_Address90_High
The MAC Address90 High register holds the upper 16 bits of the 91th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address90 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address90_Low
The MAC Address90 Low register holds the lower 32 bits of the 91th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address91_High
The MAC Address91 High register holds the upper 16 bits of the 92th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address91 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address91_Low
The MAC Address91 Low register holds the lower 32 bits of the 92th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address92_High
The MAC Address92 High register holds the upper 16 bits of the 93th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address92 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address92_Low
The MAC Address92 Low register holds the lower 32 bits of the 93th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address93_High
The MAC Address93 High register holds the upper 16 bits of the 94th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address93 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address93_Low
The MAC Address93 Low register holds the lower 32 bits of the 94th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
Altera Corporation
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on page 17-697
2016.10.28
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