Altera cyclone V Technical Reference page 1370

cv_5v4
2016.10.28
31 30
15 14
Flow_Control Fields
Bit
31:16
pt
7
dzpq
Ethernet Media Access Controller
Send Feedback
29 28 27 26
13 12 11 10
Reserved
Name
This field holds the value to be used in the Pause Time
field in the transmit control frame. Because the Pause
Time bits are double-synchronized to the (G)MII
clock domain, then consecutive writes to this register
should be performed only after at least four clock
cycles in the destination clock domain.
When this bit is set, it disables the automatic
generation of the Zero-Quanta Pause Control frames
on the de-assertion of the flow-control signal from
the FIFO layer (MTL or external sideband flow
control signal sbd_​flowctrl_​i/​mti_​flowctrl_​i)​. When
this bit is reset, normal operation with automatic
Zero-Quanta Pause Control frame generation is
enabled.
Value
0x1
0x0
Bit Fields
25 24 23 22
pt
RW 0x0
9 8 7 6
dzpq Reser
ved
RW
0x0
Description
Description
Disable Auto Gen. of Zero-Quanta Pause
Enable Auto Gen. of Zero-Quanta Pause
Flow_Control
21 20 19 18
5 4 3 2
plt up rfe
RW 0x0 RW RW
0x0 0x0
Access
RW
RW
17-155
17 16
1 0
tfe fca_bpa
RW RW 0x0
0x0
Reset
0x0
0x0
Altera Corporation