Altera cyclone V Technical Reference page 1372

Hard processor system
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cv_5v4
2016.10.28
Bit
1
tfe
0
fca_bpa
VLAN_Tag
The VLAN Tag register contains the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC
compares the 13th and 14th bytes of the receiving frame (Length/Type) with 16'h8100, and the following
two bytes are compared with the VLAN tag. If a match occurs, the MAC sets the received VLAN bit in the
receive frame status. The legal length of the frame is increased from 1,518 bytes to 1,522 bytes. Because the
VLAN Tag register is double-synchronized to the (G)MII clock domain, then consecutive writes to these
register should be performed only after at least four clock cycles in the destination clock domain.
Ethernet Media Access Controller
Send Feedback
Name
In the full-duplex mode, when this bit is set, the MAC
enables the flow control operation to transmit Pause
frames. When this bit is reset, the flow control
operation in the MAC is disabled, and the MAC does
not transmit any Pause frames. In half-duplex mode,
when this bit is set, the MAC enables the back-
pressure operation. When this bit is reset, the back-
pressure feature is disabled.
Value
0x0
0x1
This bit initiates a Pause Control frame in the full-
duplex mode and activates the backpressure function
in the half-duplex mode if the TFE bit is set. In the
full-duplex mode, this bit should be read as 1'b0
before writing to the Flow Control register. To initiate
a Pause control frame, the Application must set this
bit to 1'b1. During a transfer of the Control Frame,
this bit continues to be set to signify that a frame
transmission is in progress. After the completion of
Pause control frame transmission, the MAC resets
this bit to 1'b0. The Flow Control register should not
be written to until this bit is cleared. In the half-
duplex mode, when this bit is set (and TFE is set),
then backpressure is asserted by the MAC. During
backpressure, when the MAC receives a new frame,
the transmitter starts sending a JAM pattern resulting
in a collision. This control register bit is logically
ORed with the mti_​flowctrl_​i input signal for the
backpressure function. When the MAC is configured
for the full-duplex mode, the BPA is automatically
disabled.
Value
0x0
0x1
Description
Description
Transmit Flow Control Disable
Transmit Flow Control Enable
Description
Pause Ctrl Frame and BPA off
Init Pause Ctrl Frame and BPA
17-157
VLAN_Tag
Access
Reset
RW
0x0
RW
0x0
Altera Corporation

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