Altera cyclone V Technical Reference page 1269

Hard processor system
Hide thumbs Also See for cyclone V:
Table of Contents

Advertisement

17-54
Peer-to-Peer Transparent Clock
Table 17-20: Timestamp Snapshot Dependency on Register Bits
X is defined as a "don't care" in the table.
snaptypsel
(bits[17:16])
0x0
0x0
0x0
0x1
0x1
0x1
0x2
0x3
Peer-to-Peer Transparent Clock
The peer-to-peer transparent clock differs from the end-to-end transparent clock in the way it corrects and
handles the PTP timing messages. In all other aspects, it is identical to the end-to-end transparent clock.
In the peer-to-peer transparent clock, the computation of the link delay is based on an exchange of
Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up messages with the link peer. The residence time of
the Pdelay_Req and the associated Pdelay_resp packets is added and inserted into the correction field of
the associated Pdely_Resp_Followup packet.
Therefore, support for taking snapshot for the event messages related to Pdelay is added as shown in the
table below.
Table 17-21: Peer-to-Peer Transparent Clock: PTP Messages for Snapshot
You can take the snapshot by setting the snapshot select bits (
register.
Control
Altera Corporation
(bit 15)
tsmstrena
X
0
1
X
0
1
X
X
(bit 14)
tsevntena
0
1
1
0
1
1
X
X
PTP Messages
SYNC
Pdelay_Req
Pdelay_Resp
snaptypsel
PTP Messages
SYNC, Follow_Up, Delay_Req,
Delay_Resp
SYNC
Delay_Req
SYNC, Follow_Up, Delay_Req,
Delay_Resp, Pdelay_Req,
Pdelay_Resp, Pdelay_Resp_
Follow_Up
SYNC, Pdelay_Req, Pdelay_Resp
Delay_Req, Pdelay_Req, Pdelay_
Resp
SYNC, Delay_Req
Pdelay_Req, Pdelay_Resp
) to b'11 in the
Timestamp
Ethernet Media Access Controller
Send Feedback
cv_5v4
2016.10.28

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents