Altera cyclone V Technical Reference page 1263

17-48
Reference Timing Source
the PHY interface. This timing information must be captured and returned to the software for the proper
implementation of PTP with high accuracy.
The EMAC is intended to support IEEE 1588 operation in all modes with a resolution of 20 ns. When the
two EMACs are operating in an IEEE 1588 environment, the MPU subsystem is responsible for
maintaining synchronization between the time counters internal to the two MACs.
The IEEE 1588 interface to the FPGA allows the FPGA to provide a source for the
input as well to allow it to monitor the pulse per second output from each EMAC controller.
The EMAC component provides a hardware assisted implementation of the IEEE 1588 protocol. Hardware
support is for timestamp maintenance. Timestamps are updated when receiving any frame on the PHY
interface, and the receive descriptor is updated with this value. Timestamps are also updated when the
SFD of a frame is transmitted and the transmit descriptor is updated accordingly.
Related Information
IEEE Standards Association
For details about the IEEE 1588-2002 standard, refer to IEEE Standard 1588-2002 - IEEE Standard for a
Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, available on
the IEEE Standards Association website.
Reference Timing Source
To get a snapshot of the time, the EMAC takes the reference clock input and uses it to generate the
reference time (64-bit) internally and capture timestamps.
System Time Register Module
The 64-bit time is maintained in this module and updated using the input reference clock,
which can be the
emac_ptp_clk
input reference clock is the source for taking snapshots (timestamps) of Ethernet frames being transmitted
or received at the PHY interface.
The system time counter can be initialized or corrected using the coarse correction method. In this
method, the initial value or the offset value is written to the Timestamp Update register. For initialization,
each EMAC's system time counter is written with the value in the Timestamp Update registers, while for
system time correction, the offset value is added to or subtracted from the system time.
With the fine correction method, a slave clock's frequency drift with respect to the master clock is
corrected over a period of time instead of in one clock, as in coarse correction. This protocol helps
maintain linear time and does not introduce drastic changes (or a large jitter) in the reference time
between PTP sync message intervals.
With this method, an accumulator sums up the contents of the Timestamp_Addend register, as shown in
the figure below. The arithmetic carry that the accumulator generates is used as a pulse to increment the
system time counter. The accumulator and the addend are 32-bit registers. Here, the accumulator acts as a
high-precision frequency multiplier or divider.
Note: You must connect a PTP clock with a frequency higher than the frequency required for the
specified accuracy.
Altera Corporation
from the HPS or the
emac_ptp_clk
in the HPS is a derivative of the
†
†
†
†
†
f2s_ptp_ref_clk
and is configured in the clock manager. This
osc1_clk
emac_ptp_ref_clk
†
clk_ptp_ref
from the FPGA. The
Ethernet Media Access Controller
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