Altera cyclone V Technical Reference page 1337

17-122
GMAC Register Group Register Descriptions
MAC_Address66_High
The MAC Address66 High register holds the upper 16 bits of the 67th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address66 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address66_Low
The MAC Address66 Low register holds the lower 32 bits of the 67th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address67_High
The MAC Address67 High register holds the upper 16 bits of the 68th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address67 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address67_Low
The MAC Address67 Low register holds the lower 32 bits of the 68th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address68_High
The MAC Address68 High register holds the upper 16 bits of the 69th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address68 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address68_Low
The MAC Address68 Low register holds the lower 32 bits of the 69th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address69_High
The MAC Address69 High register holds the upper 16 bits of the 70th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address69 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address69_Low
The MAC Address69 Low register holds the lower 32 bits of the 70th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
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2016.10.28
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