Altera cyclone V Technical Reference page 1366

cv_5v4
2016.10.28
Bit
0
pr
GMII_Address
The GMII Address register controls the management cycles to the external PHY through the management
interface.
Module Instance
emac0
emac1
Offset:
0x10
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
pa
RW 0x0
GMII_Address Fields
Bit
15:11
pa
Ethernet Media Access Controller
Send Feedback
Name
When this bit is set, the Address Filter block passes all
incoming frames regardless of its destination or
source address. The SA or DA Filter Fails status bits of
the Receive Status Word are always cleared when PR
is set.
Value
0x0
0x1
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This field indicates which of the 32 possible PHY
devices are being accessed. For RevMII, this field
gives the PHY Address of the RevMII block.
Description
Description
Clear SA DA Status Bits
All Incoming Frames Passed
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
gr
RW 0x0
Description
GMII_Address
Access
RW
Register Address
0xFF700010
0xFF702010
21 20 19 18
5 4 3 2
cr
RW 0x0
Access
RW
17-151
Reset
0x0
17 16
1 0
gw gb
RW RW 0x0
0x0
Reset
0x0
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