Altera cyclone V Technical Reference page 1344

cv_5v4
2016.10.28
MAC_Address94_High
The MAC Address94 High register holds the upper 16 bits of the 95th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address94 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address94_Low
The MAC Address94 Low register holds the lower 32 bits of the 95th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address95_High
The MAC Address95 High register holds the upper 16 bits of the 96th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address95 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address95_Low
The MAC Address95 Low register holds the lower 32 bits of the 96th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address96_High
The MAC Address96 High register holds the upper 16 bits of the 97th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address96 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address96_Low
The MAC Address96 Low register holds the lower 32 bits of the 97th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address97_High
The MAC Address97 High register holds the upper 16 bits of the 98th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address97 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address97_Low
The MAC Address97 Low register holds the lower 32 bits of the 98th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
Ethernet Media Access Controller
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on page 17-713
GMAC Register Group Register Descriptions
17-129
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