Altera cyclone V Technical Reference page 1376

Hard processor system

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Ethernet Media Access Controller

Send Feedback

When high, this bit indicates that the MTL Tx FIFO

Write Controller is active and transferring data to the

This field indicates the state of the Tx FIFO Read

When high, this bit indicates that the MAC

transmitter is in the PAUSE condition (in the full-

duplex only mode) and hence does not schedule any

frame for transmission.

This field indicates the state of the MAC Transmit

Frame Controller block

Tx FIFO Write Ctrl Inactive

Tx FIFO Write Ctrl Active

Read State (transferring data to the MAC

transmitter)

Waiting for TxStatus from the MAC

Writing the received TxStatus or flushing the

MAC Transmitter Pause Disabled

MAC Transmitter Pause Condition

Waiting Prev. State or IFG

Generating Tx Pause

Tx Input Frame

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