Altera cyclone V Technical Reference page 1295

17-80
EMAC Module Address Map
Register
Layer3_Addr2_Reg2
page 17-347
Layer3_Addr3_Reg2
page 17-348
L3_L4_Control3
page 17-349
Layer4_Address3
page 17-352
Layer3_Addr0_Reg3
page 17-353
Layer3_Addr1_Reg3
page 17-354
Layer3_Addr2_Reg3
page 17-355
Layer3_Addr3_Reg3
page 17-356
Hash_Table_Reg0
page 17-357
Hash_Table_Reg1
page 17-358
Hash_Table_Reg2
page 17-359
Hash_Table_Reg3
page 17-359
Hash_Table_Reg4
page 17-360
Hash_Table_Reg5
page 17-361
Hash_Table_Reg6
page 17-361
Hash_Table_Reg7
page 17-362
VLAN_Hash_Table_Reg
on page 17-363
Timestamp_Control
page 17-363
Sub_Second_Increment
on page 17-369
System_Time_Seconds
on page 17-370
Altera Corporation
Offset Width Acces
on 0x478 32
on 0x47C 32
on 0x490 32
on 0x494 32
on 0x4A0 32
on 0x4A4 32
on 0x4A8 32
on 0x4AC 32
on 0x500 32
on 0x504 32
on 0x508 32
on 0x50C 32
on 0x510 32
on 0x514 32
on 0x518 32
on 0x51C 32
0x588 32
on 0x700 32
0x704 32
0x708 32
Reset Value
s
Register 286 (Layer 3 Address 2
RW 0x0
Register 2)
Register 287 (Layer 3 Address 3
RW 0x0
Register 2)
Register 292 (Layer 3 and Layer 4
RW 0x0
Control Register 3)
Register 293 (Layer 4 Address
RW 0x0
Register 3)
Register 296 (Layer 3 Address 0
RW 0x0
Register 3)
Register 297 (Layer 3 Address 1
RW 0x0
Register 3)
Register 298 (Layer 3 Address 2
RW 0x0
Register 3)
Register 299 (Layer 3 Address 3
RW 0x0
Register 3)
Register 320 (Hash Table Register
RW 0x0
0)
Register 321 (Hash Table Register
RW 0x0
1)
Register 322 (Hash Table Register
RW 0x0
2)
Register 323 (Hash Table Register
RW 0x0
3)
Register 324 (Hash Table Register
RW 0x0
4)
Register 325 (Hash Table Register
RW 0x0
5)
Register 326 (Hash Table Register
RW 0x0
6)
Register 327 (Hash Table Register
RW 0x0
7)
Register 354 (VLAN Hash Table
RW 0x0
Register)
Register 448 (Timestamp Control
RW 0x2000
Register)
Register 449 (Sub-Second
RW 0x0
Increment Register)
Register 450 (System Time -
RO 0x0
Seconds Register)
2016.10.28
Description
Ethernet Media Access Controller
Send Feedback
cv_5v4