Altera cyclone V Technical Reference page 1288

cv_5v4
2016.10.28
Register
Interrupt_Status
page 17-167
Interrupt_Mask
page 17-170
MAC_Address0_High
page 17-171
MAC_Address0_Low
page 17-172
MAC_Address1_High
page 17-173
MAC_Address1_Low
page 17-177
MAC_Address2_High
page 17-177
MAC_Address2_Low
page 17-181
MAC_Address3_High
page 17-181
MAC_Address3_Low
page 17-185
MAC_Address4_High
page 17-185
MAC_Address4_Low
page 17-189
MAC_Address5_High
page 17-189
MAC_Address5_Low
page 17-193
MAC_Address6_High
page 17-193
MAC_Address6_Low
page 17-197
MAC_Address7_High
page 17-197
MAC_Address7_Low
page 17-201
MAC_Address8_High
page 17-201
MAC_Address8_Low
page 17-205
Ethernet Media Access Controller
Send Feedback
Offset Width Acces
on 0x38 32
on 0x3C 32
on 0x40 32
on 0x44 32
on 0x48 32
on 0x4C 32
on 0x50 32
on 0x54 32
on 0x58 32
on 0x5C 32
on 0x60 32
on 0x64 32
on 0x68 32
on 0x6C 32
on 0x70 32
on 0x74 32
on 0x78 32
on 0x7C 32
on 0x80 32
on 0x84 32
EMAC Module Address Map
Reset Value
s
Register 14 (Interrupt Register)
RO 0x0
Register 15 (Interrupt Mask
RW 0x0
Register)
Register 16 (MAC Address0 High
RW 0x8000FFFF
Register)
Register 17 (MAC Address0 Low
RW 0xFFFFFFFF
Register)
Register 18 (MAC Address1 High
RW 0xFFFF
Register)
Register 19 (MAC Address1 Low
RW 0xFFFFFFFF
Register)
Register 20 (MAC Address2 High
RW 0xFFFF
Register)
Register 21 (MAC Address2 Low
RW 0xFFFFFFFF
Register)
Register 22 (MAC Address3 High
RW 0xFFFF
Register)
Register 23 (MAC Address3 Low
RW 0xFFFFFFFF
Register)
Register 24 (MAC Address4 High
RW 0xFFFF
Register)
Register 25 (MAC Address4 Low
RW 0xFFFFFFFF
Register)
Register 26 (MAC Address5 High
RW 0xFFFF
Register)
Register 27 (MAC Address5 Low
RW 0xFFFFFFFF
Register)
Register 28 (MAC Address6 High
RW 0xFFFF
Register)
Register 29 (MAC Address6 Low
RW 0xFFFFFFFF
Register)
Register 30 (MAC Address7 High
RW 0xFFFF
Register)
Register 31 (MAC Address7 Low
RW 0xFFFFFFFF
Register)
Register 32 (MAC Address8 High
RW 0xFFFF
Register)
Register 33 (MAC Address8 Low
RW 0xFFFFFFFF
Register)
17-73
Description
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