Altera cyclone V Technical Reference page 1322

cv_5v4
2016.10.28
Hash_Table_Reg0
This register contains the first 32 bits of the hash table. The 256-bit Hash table is used for group address
filtering. For hash filtering, the content of the destination address in the incoming frame is passed through
the CRC logic and the upper eight bits of the CRC register are used to index the content of the Hash table.
The most significant bits determines the register to be used (Hash Table Register X), and the least
significant five bits determine the bit within the register. For example, a hash value of 8b'10111111 selects
Bit 31 of the Hash Table Register 5. The hash value of the destination address is calculated in the following
way: 1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate
CRC32). 2. Perform bitwise reversal for the value obtained in Step 1. 3. Take the upper 8 bits from the
value obtained in Step 2. If the corresponding bit value of the register is 1'b1, the frame is accepted.
Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register 1 (MAC Frame Filter), then all
multicast frames are accepted regardless of the multicast hash values. Because the Hash Table register is
double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24]
(in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are
written. Note: Because of double-synchronization, consecutive writes to this register should be performed
after at least four clock cycles in the destination clock domain.
Hash_Table_Reg1
This register contains the second 32 bits of the hash table.
Hash_Table_Reg2
This register contains the third 32 bits of the hash table.
Hash_Table_Reg3
This register contains the fourth 32 bits of the hash table.
Hash_Table_Reg4
This register contains the fifth 32 bits of the hash table.
Hash_Table_Reg5
This register contains the sixth 32 bits of the hash table.
Hash_Table_Reg6
This register contains the seventh 32 bits of the hash table.
Hash_Table_Reg7
This register contains the eighth 32 bits of the hash table.
VLAN_Hash_Table_Reg
The 16-bit Hash table is used for group address filtering based on VLAN tag when Bit 18 (VTHM) of
Register 7 (VLAN Tag Register) is set. For hash filtering, the content of the 16-bit VLAN tag or 12-bit
VLAN ID (based on Bit 16 (ETV) of VLAN Tag Register) in the incoming frame is passed through the
CRC logic and the upper four bits of the calculated CRC are used to index the contents of the VLAN Hash
table. For example, a hash value of 4b'1000 selects Bit 8 of the VLAN Hash table. The hash value of the
destination address is calculated in the following way: 1. Calculate the 32-bit CRC for the VLAN tag or ID
(See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32). 2. Perform bitwise reversal for the value
obtained in Step 1. 3. Take the upper four bits from the value obtained in Step 2. If the corresponding bit
value of the register is 1'b1, the frame is accepted. Otherwise, it is rejected. Because the Hash Table register
is double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[15:8]
(in little-endian mode) or Bits[7:0] (in big-endian mode) of this register are written. Notes: * Because of
double-synchronization, consecutive writes to this register should be performed after at least four clock
cycles in the destination clock domain.
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GMAC Register Group Register Descriptions
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