Altera cyclone V Technical Reference page 1368

Hard processor system

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The GMII Data register stores Write data to be written to the PHY register located at the address specified

in Register 4 (GMII Address Register). This register also stores the Read data from the PHY register

located at the address specified by Register 4.

Module Instance

Ethernet Media Access Controller

Send Feedback

When set, this bit indicates to the PHY or RevMII

that this is a Write operation using the GMII Data

Read operation, that is, placing the data in the GMII

Data register.

This bit should read logic 0 before writing to Register

4 and Register 5. During a PHY or RevMII register

access, the software sets this bit to 1'b1 to indicate that

a Read or Write access is in progress. The Register 5 is

invalid until this bit is cleared by the MAC. Therefore,

MAC clears this bit during a PHY Write operation.

Similarly for a read operation, the contents of Register

5 are not valid until this bit is cleared. The subsequent

read or write operation should happen only after the

previous operation is complete. Because there is no

acknowledgment from the PHY to MAC after a read

or write operation is completed, there is no change in

the functionality of this bit even when the PHY is not

GMII Read Operation

GMII Write Operation

Base Address

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