Altera cyclone V Technical Reference page 1381

Hard processor system

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LPI_Timers_Control

LPI_Timers_Control

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for

which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the

normal transmission.

Module Instance

Altera Corporation

When set, this bit indicates that the MAC Receiver

has received an LPI pattern and entered the LPI state.

This bit is cleared by a read into this register. Note:

This bit may not get set if the MAC stops receiving the

LPI pattern for a very short duration, such as, less

than 3 clock cycles of l3_sp_clk.

When set, this bit indicates that the MAC transmitter

has exited the LPI state after the user has cleared the

LPIEN bit and the LPI TW Timer has expired. This

bit is cleared by a read into this register.

When set, this bit indicates that the MAC Transmitter

has entered the LPI state because of the setting of the

LPIEN bit. This bit is cleared by a read into this

MAC Receiver Not In LPI State

MAC Receiver In LPI State

MAC Transmitter Non LPI State

MAC Transmitter Exited LPI State

MAC Transmitter Not in LPI State

MAC Transmitter Entered LPI State

Base Address

Ethernet Media Access Controller

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