Altera cyclone V Technical Reference page 1365

Hard processor system
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MAC_Frame_Filter
Bit
4
pm
3
daif
2
hmc
1
huc
Altera Corporation
Name
When set, this bit indicates that all received frames
with a multicast destination address (first bit in the
destination address field is '1') are passed. When reset,
filtering of multicast frame depends on HMC bit.
Value
0x0
0x1
When this bit is set, the Address Check block operates
in inverse filtering mode for the DA address
comparison for both unicast and multicast frames.
When reset, normal filtering of frames is performed.
Value
0x0
0x1
When set, MAC performs destination address filtering
of received multicast frames according to the hash
table. When reset, the MAC performs a perfect
destination address filtering for multicast frames, that
is, it compares the DA field with the values
programmed in DA registers.
Value
0x0
0x1
When set, MAC performs destination address filtering
of unicast frames according to the hash table. When
reset, the MAC performs a perfect destination address
filtering for unicast frames, that is, it compares the DA
field with the values programmed in DA registers.
Value
0x0
0x1
Description
Description
Allows Filter of MC Frames
All Rcvd MC Frames Pass
Description
Normal Inverse Filter
Address Check Block Inverse Filter
Description
MAC Filters with Compare
MAC Filters with Hash Table
Description
MAC Filters with Compare
MAC Filters with Hash Table
2016.10.28
Access
Reset
RW
0x0
RW
0x0
RW
0x0
RW
0x0
Ethernet Media Access Controller
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cv_5v4

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