Altera cyclone V Technical Reference page 1346

cv_5v4
2016.10.28
MAC_Address102_High
The MAC Address102 High register holds the upper 16 bits of the 103th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address102 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address102_Low
The MAC Address102 Low register holds the lower 32 bits of the 103th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address103_High
The MAC Address103 High register holds the upper 16 bits of the 104th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address103 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address103_Low
The MAC Address103 Low register holds the lower 32 bits of the 104th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address104_High
The MAC Address104 High register holds the upper 16 bits of the 105th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address104 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address104_Low
The MAC Address104 Low register holds the lower 32 bits of the 105th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address105_High
The MAC Address105 High register holds the upper 16 bits of the 106th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address105 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address105_Low
The MAC Address105 Low register holds the lower 32 bits of the 106th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
Ethernet Media Access Controller
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on page 17-729
on page 17-733
on page 17-733
on page 17-737
on page 17-737
on page 17-741
on page 17-741
on page 17-745
GMAC Register Group Register Descriptions
17-131
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