Altera cyclone V Technical Reference page 1352

cv_5v4
2016.10.28
MAC_Address126_High
The MAC Address126 High register holds the upper 16 bits of the 127th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address126 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address126_Low
The MAC Address126 Low register holds the lower 32 bits of the 127th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address127_High
The MAC Address127 High register holds the upper 16 bits of the 128th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address127 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address127_Low
The MAC Address127 Low register holds the lower 32 bits of the 128th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Configuration
The MAC Configuration register establishes receive and transmit operating modes.
Module Instance
emac0
emac1
Offset:
0x0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Ethernet Media Access Controller
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on page 17-825
on page 17-829
on page 17-829
on page 17-833
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
17-137
MAC_Configuration
Register Address
0xFF700000
0xFF702000
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