Altera cyclone V Technical Reference page 1351

17-136
GMAC Register Group Register Descriptions
MAC_Address122_High
The MAC Address122 High register holds the upper 16 bits of the 123th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address122 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address122_Low
The MAC Address122 Low register holds the lower 32 bits of the 123th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address123_High
The MAC Address123 High register holds the upper 16 bits of the 124th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address123 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address123_Low
The MAC Address123 Low register holds the lower 32 bits of the 124th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address124_High
The MAC Address124 High register holds the upper 16 bits of the 125th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address124 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address124_Low
The MAC Address124 Low register holds the lower 32 bits of the 125th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address125_High
The MAC Address125 High register holds the upper 16 bits of the 126th 6-byte MAC address of the
station. Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address125 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address125_Low
The MAC Address125 Low register holds the lower 32 bits of the 126th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
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2016.10.28
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