Altera cyclone V Technical Reference page 1385

17-170
Interrupt_Mask
Bit
1
pcslchgis
0
rgsmiiis
Interrupt_Mask
The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding
event in the Interrupt Status Register. The interrupt signal is sbd_intr_o.
Module Instance
emac0
emac1
Offset:
0x3C
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
Reserved
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Name
This bit is set because of any change in Link Status in
the TBI, RTBI, or SGMII PHY interface (Bit 2 in
Register 49 (AN Status Register)). This bit is cleared
when you perform a read operation on the AN Status
register. This bit is valid only when you select the
SGMII PHY interface during operation.
This bit is set because of any change in value of the
Link Status of RGMII or SMII interface (Bit 3 in
Register 54 (SGMII/RGMII/SMII Status Register)).
This bit is cleared when you perform a read operation
on the SGMII/RGMII/SMII Status Register.
0x0
0x1
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
lpiim
RW
0x0
Description
Value Description
Link No Change
Link Change
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
tsim Reserved
RW
0x0
Access
Register Address
0xFF70003C
0xFF70203C
21 20 19 18
5 4 3 2
pcsan
cim
RO
0x0
Ethernet Media Access Controller
cv_5v4
2016.10.28
Reset
RO 0x0
RO 0x0
17 16
1 0
pcslc rgsmiiim
hgim
RW 0x0
RO
0x0
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