Altera cyclone V Technical Reference page 1324

cv_5v4
2016.10.28
Auxiliary_Timestamp_Nanoseconds
This register, along with Register 461 (Auxiliary Timestamp Seconds Register), gives the 64-bit timestamp
stored as auxiliary snapshot. The two registers together form the read port of a 64-bit wide FIFO with a
depth of 16. Multiple snapshots can be stored in this FIFO. The ATSNS bits in the Timestamp Status
register indicate the fill-level of this FIFO. The top of the FIFO is removed only when the last byte of
Register 461 (Auxiliary Timestamp - Seconds Register) is read. In the little-endian mode, this means when
Bits[31:24] are read. In big-endian mode, it corresponds to the reading of Bits[7:0] of Register 461
(Auxiliary Timestamp - Seconds Register).
Auxiliary_Timestamp_Seconds
Contains the higher 32 bits (Seconds field)​ of the auxiliary timestamp.
PPS0_Interval
The PPS0 Interval register contains the number of units of sub-second increment value between the rising
edges of PPS0 signal output (ptp_pps_o[0]).
PPS0_Width
The PPS0 Width register contains the number of units of sub-second increment value between the rising
and corresponding falling edges of the PPS0 signal output (ptp_pps_o[0]).
MAC_Address16_High
The MAC Address16 High register holds the upper 16 bits of the 17th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address16 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address16_Low
The MAC Address16 Low register holds the lower 32 bits of the 17th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address17_High
The MAC Address17 High register holds the upper 16 bits of the 18th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address17 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address17_Low
The MAC Address17 Low register holds the lower 32 bits of the 18th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
Ethernet Media Access Controller
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GMAC Register Group Register Descriptions
on page 17-382
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