Altera cyclone V Technical Reference page 1356

cv_5v4
2016.10.28
Bit
14
fes
13
do
12
lm
11
dm
Ethernet Media Access Controller
Send Feedback
Name
This bit selects the speed in the RGMII interface: * 0:
10 Mbps * 1: 100 Mbps This bit generates link speed
encoding when TC (Bit 24) is set in the RGMII, SMII,
or SGMII mode.
Value
0x0
0x1
When this bit is set, the MAC disables the reception
of frames when the gmii_txen_o is asserted in the
half-duplex mode. When this bit is reset, the MAC
receives all packets that are given by the PHY while
transmitting. This bit is not applicable if the MAC is
operating in the full-duplex mode.
Value
0x0
0x1
When this bit is set, the MAC operates in the
loopback mode at GMII or MII. The (G)MII Receive
clock input is required for the loopback to work
properly, because the Transmit clock is not looped-
back internally.
Value
0x0
0x1
When this bit is set, the MAC operates in the full-
duplex mode where it can transmit and receive
simultaneously.
Value
0x1
0x0
Description
Description
Speed = 10 Mbps
Speed = 100 Mbps
Description
MAC Enables Reception of Frames
MAC Disables Reception of Frames
Description
Disable Loop Back
Enable Loop Back
Description
MAC Full Duplex Enabled
MAC Full Duplex Disabled
17-141
MAC_Configuration
Access Reset
RW 0x0
RW 0x0
RW 0x0
RW 0x0
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