Altera cyclone V Technical Reference page 1308

cv_5v4
2016.10.28
DMA Register Group
Register
Bus_Mode on page 17-
835
Transmit_Poll_Demand
on page 17-839
Receive_Poll_Demand
on page 17-840
Receive_Descriptor_Li
st_Address on page
17-841
Transmit_Descriptor_L
ist_Address on page
17-842
Status on page 17-843
Operation_Mode
page 17-848
Interrupt_Enable
page 17-855
Missed_Frame_And_Buff
er_Overflow_Counter
on page 17-859
Receive_Interrupt_Wat
chdog_Timer on page
17-861
AXI_Bus_Mode
17-861
AHB_or_AXI_Status
page 17-864
Current_Host_Transmit
_Descriptor on page
17-865
Current_Host_Receive_
Descriptor on page
17-866
Current_Host_Transmit
_Buffer_Address
page 17-866
Current_Host_Receive_
Buffer_Address
page 17-867
Ethernet Media Access Controller
Send Feedback
Offset Width Acces
0x1000
0x1004
0x1008
0x100C
0x1010
0x1014
on 0x1018
on 0x101C
0x1020
0x1024
on page 0x1028
on 0x102C
0x1048
0x104C
0x1050
on
0x1054
on
Reset Value
s
32 RW 0x20101
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RW 0x0
32 RO 0x0
32 RW 0x0
32 RW 0x110001
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
EMAC Module Address Map
Description
Register 0 (Bus Mode Register)
Register 1 (Transmit Poll Demand
Register)
Register 2 (Receive Poll Demand
Register)
Register 3 (Receive Descriptor List
Address Register)
Register 4 (Transmit Descriptor
List Address Register)
Register 5 (Status Register)
Register 6 (Operation Mode
Register)
Register 7 (Interrupt Enable
Register)
Register 8 (Missed Frame and
Buffer Overflow Counter Register)
Register 9 (Receive Interrupt
Watchdog Timer Register)
Register 10 (AXI Bus Mode
Register)
Register 11 (AHB or AXI Status
Register)
Register 18 (Current Host
Transmit Descriptor Register)
Register 19 (Current Host Receive
Descriptor Register)
Register 20 (Current Host
Transmit Buffer Address Register)
Register 21 (Current Host Receive
Buffer Address Register)
Altera Corporation
17-93