Altera cyclone V Technical Reference page 1314

cv_5v4
2016.10.28
MAC_Address14_Low
The MAC Address14 Low register holds the lower 32 bits of the 15th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
MAC_Address15_High
The MAC Address15 High register holds the upper 16 bits of the 16th 6-byte MAC address of the station.
Because the MAC address registers are configured to be double-synchronized to the (G)MII clock
domains, the synchronization is triggered only when bits[31:24] (in little-endian mode) or Bits[7:0] (in
big-endian mode) of the MAC Address15 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain. Note that all MAC Address High registers (except MAC Address0 High)
have the same format.
MAC_Address15_Low
The MAC Address15 Low register holds the lower 32 bits of the 16th 6-byte MAC address of the station.
Note that all MAC Address Low registers (except MAC Address0 Low) have the same format.
SGMII_RGMII_SMII_Control_Status
The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface
(selected at reset) from the PHY.
MMC_Control
The MMC Control register establishes the operating mode of the management counters. Note: The bit 0
(Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set
both bits in the same write cycle, all counters are cleared and the bit 4 is not set.
MMC_Receive_Interrupt
The MMC Receive Interrupt register maintains the interrupts that are generated when the following
happens: * Receive statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter
and 0x8000 for 16-bit counter). * Receive statistic counters cross their maximum values (0xFFFF_FFFF for
32-bit counter and 0xFFFF for 16-bit counter). When the Counter Stop Rollover is set, then interrupts are
set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An
interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least
significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
MMC_Transmit_Interrupt
The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters
reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and
the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter
Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Transmit
Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter
that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must
be read in order to clear the interrupt bit.
MMC_Receive_Interrupt_Mask
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the
receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits
wide.
MMC_Transmit_Interrupt_Mask
The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the
transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits
wide.
Ethernet Media Access Controller
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GMAC Register Group Register Descriptions
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