Altera cyclone V Technical Reference page 1380

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

Ethernet Media Access Controller

Send Feedback

When set, this bit instructs the MAC Transmitter to

enter the LPI state. When reset, this bit instructs the

MAC to exit the LPI state and resume normal

transmission. This bit is cleared when the LPITXA bit

is set and the MAC exits the LPI state because of the

arrival of a new packet for transmission.

When set, this bit indicates that the MAC is receiving

the LPI pattern on the GMII or MII interface.

When set, this bit indicates that the MAC is transmit‐

ting the LPI pattern on the GMII or MII interface.

When set, this bit indicates that the MAC Receiver

has stopped receiving the LPI pattern on the GMII or

MII interface, exited the LPI state, and resumed the

normal reception. This bit is cleared by a read into

this register. Note: This bit may not get set if the MAC

stops receiving the LPI pattern for a very short

duration, such as, less than 3 clock cycles of l3_sp_clk.

MAC Transmitter exit LPI State

MAC Transmitter enters LPI State

MAC is not receiving LPI Pattern

MAC receiving LPI Pattern

MAC Transmitting LPI Pattern

MAC RX receiving LPI Patterns

MAC RX Stopped receiving LPI Patterns

LPI_Control_Status

Altera Corporation

Show Quick Links

Table of Contents