Altera cyclone V Technical Reference page 1387

17-172
MAC_Address0_Low
0x665544332211. Because the MAC address registers are double-synchronized to the (G)MII clock
domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0]
(in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates,
the consecutive writes to this Address Low Register should be performed after at least four clock cycles in
the destination clock domain.
Module Instance
emac0
emac1
Offset:
0x40
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
ae
RO 0x1
15 14
MAC_Address0_High Fields
Bit
31
ae
15:0
addrhi
MAC_Address0_Low
The MAC Address0 Low register holds the lower 32 bits of the first 6-byte MAC address of the station.
Module Instance
emac0
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This bit is always set to 1.
This field contains the upper 16 bits (47:32) of the first
6-byte MAC address. The MAC uses this field for
filtering the received frames and inserting the MAC
address in the Transmit Flow Control (PAUSE)
Frames.
Base Address
0xFF700000
0xFF702000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
addrhi
RW 0xFFFF
Description
Base Address
0xFF700000
Register Address
0xFF700040
0xFF702040
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700044
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x1
RW 0xFFFF
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