Altera cyclone V Technical Reference page 1369

17-154
Flow_Control
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
GMII_Data Fields
Bit
15:0
gd
Flow_Control
The Flow Control register controls the generation and reception of the Control (Pause Command) frames
by the MAC's Flow control block. A Write to a register with the Busy bit set to '1' triggers the Flow Control
block to generate a Pause Control frame. The fields of the control frame are selected as specified in the
802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the
control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host
must make sure that the Busy bit is cleared before writing to the register.
Module Instance
emac0
emac1
Offset:
0x18
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Name
This field contains the 16-bit data value read from the
PHY or RevMII after a Management Read operation
or the 16-bit data value to be written to the PHY or
RevMII before a Management Write operation.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
Reserved
9 8 7 6
gd
RW 0x0
Description
Base Address
0xFF700000
0xFF702000
21 20 19 18
5 4 3 2
Access
Register Address
0xFF700018
0xFF702018
Ethernet Media Access Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
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