Altera cyclone V Technical Reference page 1360

cv_5v4
2016.10.28
Bit
1:0
prelen
MAC_Frame_Filter
The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from
this register go to the address check block of the MAC, which performs the first level of address filtering.
The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad
Frames and Pass Control Frames.
Module Instance
emac0
emac1
Offset:
0x4
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
ra
RW 0x0
15 14
Reserved
Ethernet Media Access Controller
Send Feedback
Name
These bits control the number of preamble bytes that
are added to the beginning of every Transmit frame.
The preamble reduction occurs only when the MAC
is operating
Value
0x0
0x1
0x2
0xFF700000
0xFF702000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
Reserved
13 12 11 10
hpf
RW
0x0
Description
Description
Preamble 7 Bytes
Preamble 5 Bytes
Preamble 3 Bytes
Base Address
Bit Fields
25 24 23 22
9 8 7 6
saf saif pcf
RW RW RW 0x0
0x0 0x0
MAC_Frame_Filter
Access
Register Address
0xFF700004
0xFF702004
21 20 19 18
dntu ipfe Reserved
RW RW
0x0 0x0
5 4 3 2
dbf pm daif hmc
RW RW RW RW
0x0 0x0 0x0 0x0
17-145
Reset
RW 0x0
17 16
vtfe
RW 0x0
1 0
huc pr
RW RW 0x0
0x0
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