Altera cyclone V Technical Reference page 1279

17-64
System Level EMAC Configuration Registers
Table 17-24: System Manager Clock and Interface Settings
Register.Field
ctrl.ptpclksel_0
ctrl.ptpclksel_1
ctrl.physel_0
ctrl.physel_1
The following table summarizes the important System Manager configuration register bits. All of the
fields, except the AXI cache settings, are assumed to be static and must be set before the EMAC is brought
out of reset. If the FPGA interface is used, the FPGA must be in user mode and enabled with the
appropriate clock signals active before the EMAC can be brought out of reset.
Table 17-25: System Manager Static Control Settings
Register.Field
module.emac_0
module.emac_1
l3master.awcache
_1
l3master.awcache
_0
l3master.arcache
_1
l3master.arcache
_0
Various registers within the Clock Manager must also be configured in order for the EMAC controller to
perform properly.
Altera Corporation
1588 PTP reference clock. This bit selects the soure of the 1588 PTP reference clock.
• 0x0= (default from Clock Manager)
osc1_clk
• 0x1=
fpga_ptp_ref_clk
usermode with an active reference clock)
PHY Interface Select. These two bits set the PHY mode.
• 0x0= GMII or MII
• 0x1= RGMII
• ox2= RMII (default)
Note: Selecting the 0x0 encoding routes the GMII/MII signals to the FPGA
fabric only and selecting the 0x1 encoding routes the RGMII signals to
the HPS only. 0x2 is not a valid encoding and depending on the interface
selected, must be changed to 0x0 or 0x1 out of reset.
FPGA interface to EMAC disable. This field is used to disable signals from the
FPGA to the EMAC modules that could potentially interfere with their normal
operation
• 0x0= Disable (default)
• 0x1=Enable
EMAC AXI Master AxCACHE settings. It is recommended that these bits are set
while the EMAC is idle or in reset.
Description
(from FPGA fabric; in this case, the FPGA must be in
Description
2016.10.28
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