Altera cyclone V Technical Reference page 1320

cv_5v4
2016.10.28
Layer4_Address0
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian
mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you
should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four
clock cycles delay of the destination clock.
Layer3_Addr0_Reg0
For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source Address field. For IPv6
frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr1_Reg0
For IPv4 frames, the Layer 3 Address 1 Register 0 contains the 32-bit IP Destination Address field. For
IPv6 frames, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr2_Reg0
For IPv4 frames, the Layer 3 Address 2 Register 0 is reserved. For IPv6 frames, it contains Bits [95:64] of
the 128-bit IP Source Address or Destination Address field.
Layer3_Addr3_Reg0
For IPv4 frames, the Layer 3 Address 3 Register 0 is reserved. For IPv6 frames, it contains Bits [127:96] of
the 128-bit IP Source Address or Destination Address field.
L3_L4_Control1
This register controls the operations of the filter 0 of Layer 3 and Layer 4.
Layer4_Address1
Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then
the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian
mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you
should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four
clock cycles delay of the destination clock.
Layer3_Addr0_Reg1
For IPv4 frames, the Layer 3 Address 0 Register 1 contains the 32-bit IP Source Address field. For IPv6
frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.
Layer3_Addr1_Reg1
For IPv4 frames, the Layer 3 Address 1 Register 1 contains the 32-bit IP Destination Address field. For
IPv6 frames, it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field
Layer3_Addr2_Reg1
For IPv4 frames, the Layer 3 Address 2 Register 1 is reserved. For IPv6 frames, it contains Bits [95:64] of
the 128-bit IP Source Address or Destination Address field.
Layer3_Addr3_Reg1
For IPv4 frames, the Layer 3 Address 3 Register 1 is reserved. For IPv6 frames, it contains Bits [127:96] of
the 128-bit IP Source Address or Destination Address field.
L3_L4_Control2
This register controls the operations of the filter 2 of Layer 3 and Layer 4.
Ethernet Media Access Controller
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GMAC Register Group Register Descriptions
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