Altera cyclone V Technical Reference page 1367

17-152
GMII_Address
Bit
10:6
gr
5:2
cr
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Name
These bits select the desired GMII register in the
selected PHY device. For RevMII, these bits select the
desired CSR register in the RevMII Registers set.
The CSR Clock Range selection determines the
frequency of the MDC clock according to the l4_mp_
clk frequency used in your design. The suggested
range of l4_mp_clk frequency applicable for each
value (when Bit[5] = 0) ensures that the MDC clock is
approximately between the frequency range 1.0 MHz
- 2.5 MHz. When Bit 5 is set, you can achieve MDC
clock of frequency higher than the IEEE 802.3
specified frequency limit of 2.5 MHz and program a
clock divider of lower value. For example, when l4_
mp_clk is of 100 MHz frequency and you program
these bits as 1010, then the resultant MDC clock is of
12.5 MHz which is outside the limit of IEEE 802.3
specified range. Only use the values larger than 7 if
the interfacing chips support faster MDC clocks.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x8
0x9
0xa
0xb
0xc
0xd
0xe
0xf
Description
Description
l4_mp_clk 60-100Mhz and MDC clock = l4_
mp_clk/42
l4_mp_clk 100-150Mhz and MDC clock =
l4_mp_clk/62
l4_mp_clk 25-35Mhz and MDC clock = l4_
mp_clk/16
l4_mp_clk 35-60Mhz and MDC clock = l4_
mp_clk/26
l4_mp_clk 150-250Mhz and MDC clock =
l4_mp_clk/102
l4_mp_clk 250-300Mhz and MDC clock =
l4_mp_clk/124
l4_mp_clk/4
l4_mp_clk/6
l4_mp_clk/8
l4_mp_clk/10
l4_mp_clk/12
l4_mp_clk/14
l4_mp_clk/16
l4_mp_clk/18
2016.10.28
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RW 0x0
RW 0x0
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