Transceiver Performance Specifications - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics

Transceiver Performance Specifications

Table 1–21
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)
Symbol/
Conditions
Description
Reference Clock
Supported I/O
Standards
Input frequency
from REFCLK input
pins
Spread-spectrum Physical interface
modulating clock for PCI Express
frequency (PIPE) mode
Spread-spectrum
PIPE mode
downspread
Peak-to-peak
differential input
voltage
V (AC coupled)
ICM
HCSL I/O
V (DC coupled) standard for PCIe
ICM
reference clock
Transmitter REFCLK
(1)
Phase Noise
Frequency offset
= 1 MHz – 8 MHZ
Transmitter REFCLK
(1)
Total Jitter
R
ref
Transceiver Clock
cal_blk_clk clock
frequency
fixedclk clock PCIe Receiver
frequency Detect
Dynamic
reconfig_clk
reconfiguration
clock frequency
clock frequency
Delta time between
reconfig_clk
Transceiver block
minimum
power-down pulse
width
December 2016 Altera Corporation
lists the Cyclone IV GX transceiver specifications.
C6
Min Typ
1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL
— 50 —
30 —
0 to
—
– 0.5%
— 0.1 —
— 1100 ± 5%
250 —
— —
— —
2000
— —
± 1%
— 10 —
— 125
2.5/
37.5 —
(2)
— — —
— — 1
C7, I7
Max Min Typ
156.25 50 — 156.25
33 30 —
0 to
— —
– 0.5%
1.6 0.1 —
1100 ± 5%
550 250 —
– 123 — —
42.3 — —
2000
— —
± 1%
125 10 —
— — 125
2.5/
50 37.5 —
(2)
2 — —
— — 1
1–17
C8
Max Min Typ Max
50 — 156.25
33 30 —
0 to
— —
– 0.5%
1.6 0.1 — 1.6
1100 ± 5%
550 250 — 550
– 123 — — – 123
42.3 — — 42.3
2000
— —
± 1%
125 10 — 125
— — 125
2.5/
50 37.5 —
(2)
2 — —
— — 1
Cyclone IV Device Handbook,
Volume 3
Unit
MHz
33 kHz
— —
V
mV
mV
dBc/Hz
ps

—
MHz
— MHz
50 MHz
2 ms
— µs