External Memory Performance; Hps External Memory Performance; Memory Interface Pin Support In Cyclone V Devices - Altera Cyclone V Device Handbook

6-2

External Memory Performance

External Memory Performance
Table 6-2: External Memory Interface Performance in Cyclone V Devices
The maximum and minimum operating frequencies depend on the memory interface standards and the supported
delay-locked loop (DLL) frequency listed in the device datasheet.
Interface
DDR3 SDRAM
DDR2 SDRAM
LPDDR2 SDRAM
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system performance specification, use
Altera's External Memory Interface Spec Estimator tool.
Cyclone V Device Datasheet

HPS External Memory Performance

Table 6-3: HPS External Memory Interface Performance
The hard processor system (HPS) is available in Cyclone V SoC devices only.
Interface
DDR3 SDRAM
DDR2 SDRAM
LPDDR2 SDRAM
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system performance specification, use Altera's
External Memory Interface Spec Estimator tool.

Memory Interface Pin Support in Cyclone V Devices

In the Cyclone V devices, the memory interface circuitry is available in every I/O bank that does not support
transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.
The memory clock pins are generated with double data rate input/output (DDRIO) registers.
Altera Corporation
Maximum Frequency (MHz)
Voltage
(V)
Hard Controller
1.5 400
1.35 400
1.8 400
1.2 333
Voltage (V)
1.5
1.35
1.8
1.2
Minimum Frequency (MHz)
Soft Controller
303
303
300
300
HPS Hard Controller (MHz)
400
400
400
333
External Memory Interfaces in Cyclone V Devices
CV-52006
2014.01.10
303
303
167
167
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