Memory; Ddr3 Sdram - Altera Arria V GX Reference Manual

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Reference manual (62 pages)

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Table of Contents

Chapter 2: Board Components

Memory

DDR3 SDRAM

Table 2–43. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)

Board Reference

DDR3 x16 (U11)

September 2015 Altera Corporation

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This section describes the starter board's memory interface support and also their

signal names, types, and connectivity relative to the Arria V GX. The starter board has

the following memory interfaces:

DDR3 SDRAM

■

Synchronous SRAM

■

Synchronous flash

For more information about the memory interfaces, refer to the following documents:

■

Timing Analysis

■

DDR, DDR2, and DDR3 SDRAM Design Tutorials

External Memory Interface Handbook.

The starter board supports a 8Mx32x8 bank DDR3 SDRAM interface for very

high-speed sequential memory access. The 32-bit data bus consists of two x16 devices

with a single address or command bus. This interface connects to the vertical I/O

banks on the top edge of the FPGA.

This DDR3 SDRAM has two interface options. The first option is a x32 interface using

a hard memory controller. The second option is a x32 interface using a soft memory

controller.

With a hard memory controller, this interface runs at the target frequency of 533 MHz

for a maximum theoretical bandwidth of 33.31 Gbps. With a soft memory controller,

this interface runs at the target frequency of 667 MHz for a maximum theoretical

bandwidth of 41.66 Gbps. Though a soft memory controller runs at higher data rate

than a hard memory controller, the hard memory controller operates at a much higher

efficiency. The maximum frequency for the Micron device is 667 MHz with a CAS

latency of 9.

Table 2–43

lists the DDR3 pin assignments, signal names, and functions. The signal

names and types are relative to the Arria V GX in terms of I/O setting and direction.

Schematic

Signal Name

DDR3_A0

DDR3_A1

DDR3_A2

DDR3_A3

DDR3_A4

DDR3_A5

DDR3_A6

section in volume 4 of the External Memory Interface Handbook.

Arria V GX

I/O Standard

Pin Number

D26

1.5-V SSTL Class I

E27

1.5-V SSTL Class I

A27

1.5-V SSTL Class I

B27

1.5-V SSTL Class I

G26

1.5-V SSTL Class I

H26

1.5-V SSTL Class I

K27

1.5-V SSTL Class I

section in volume 6 of the

Description

Address bus

Arria V GX Starter Board

Reference Manual

2–39

Table of Contents

Memory; Ddr3 Sdram - Altera Arria V GX Reference Manual

Memory

DDR3 SDRAM

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