Sdram Controller Subsystem Programming Model; Hps Memory Interface Architecture - Altera Cyclone V Device Handbook

cv_54008
2013.12.30
Name
Read Data Channel Signals
RID
RDATA
RRESP
RLAST
RVALID
RREADY
Related Information
www.arm.com
AMBA Open Specifications, including information about the AXI-3 interface

SDRAM Controller Subsystem Programming Model

SDRAM controller configuration occurs through software programming of the configuration registers using
the CSR interface.
Initialization
Initialization of the SDRAM controller has two separate regions with different controls.
Timing Parameters
The SDRAM controller supports a complete set of timing parameters, configurable at run time.

HPS Memory Interface Architecture

The configuration and initialization of the memory interface by the ARM processor is a significant difference
compared to the FPGA memory interfaces, and results in several key differences in the way the HPS memory
interface is defined and configured.
Boot-up configuration of the HPS memory interface is handled by the initial software boot code, not by the
FPGA programmer, as is the case for the FPGA memory interfaces. The Quartus II software is involved in
defining the configuration of I/O ports which is used by the boot-up code, as well as timing analysis of the
memory interface. Therefore, the memory interface must be configured with the correct PHY-level timing
information. Although configuration of the memory interface in Qsys is still necessary, it is limited to PHY-
and board-level settings.
SDRAM Controller Subsystem
Send Feedback
Bits
4
32, 64, 128 or 256
2
1
1
1
SDRAM Controller Subsystem Programming Model
Direction
Out Read data transfer ID
Out Read data
Out Read response status
Out Last transfer in a burs
Out Indicates read data is valid
In Read data channel ready signal
8-23
Function
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