Altera cyclone V Technical Reference page 1458

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

MMC_Transmit_Interrupt

The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters

reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and

the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter

Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Transmit

Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter

that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must

be read in order to clear the interrupt bit.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

Ethernet Media Access Controller

Send Feedback

This bit is set when the rxframecount_bg counter

reaches half of the maximum value or the maximum

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

Preset All Counters to almost-half

Present All Counters almost-full

Base Address

MMC_Transmit_Interrupt

Altera Corporation

Show Quick Links

Table of Contents